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1/39 august 2004 m25p20 2 mbit, low voltage, serial flash memory with 40mhz spi bus interface features summary 2 mbit of flash memory page program (up to 256 bytes) in 1.4ms (typical) sector erase (512 kbit) in 1s (typical) bulk erase (2 mbit) in 3s (typical) 2.7 to 3.6v single supply voltage spi bus compatible serial interface 40mhz clock rate (maximum) deep power-down mode 1 a (typical) electronic signature (11h) figure 1. packages so8 (mn) 150 mil width 8 1 vdfpn8 (mp) (mlp8)
m25p20 2/39 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. so and vdfpn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data output (q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip select (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 hold (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write protect (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. bus master and memory devices on the spi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 active power, stand-by power and deep power-down modes. . . . . . . . . . . . . . . . . . . . . . . . . . 8 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 srwd bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. write enable (wren) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/39 m25p20 write disable (wrdi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read status register (rdsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 srwd bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10.read status register (rdsr) instruction sequence and data-out sequence . . . . . . . 14 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11.write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read data bytes (read). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12.read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . 17 read data bytes at higher speed (fast_read). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13.read data bytes at higher speed (fast_read) instruction sequence and data-out se- quence 18 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14.page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15.sector erase (se) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16.bulk erase (be) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17.deep power-down (dp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 release from deep power-down and read electronic signature (res) . . . . . . . . . . . . . . . . . 23 figure 18.release from deep power-down and read electronic signature (res) instruction se- quence and data-out sequence23 figure 19.release from deep power-down (res) instruction sequence . . . . . . . . . . . . . . . . . . . . 24 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 20.power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. power-up timing and vwi threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. dc characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. instruction times (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
m25p20 4/39 table 15. instruction times (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 21.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. ac characteristics (25mhz operation, device grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . 31 table 18. ac characteristics (40mhz operation, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22.serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23.write protect setup and hold timing during wrsr when srwd=1 . . . . . . . . . . . . . . . 33 figure 24.hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25.output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 26.so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . 35 table 19. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data 35 figure 27.mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package outline . . . . . . . 36 table 20. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package mechanical data36 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5/39 m25p20 summary description the m25p20 is a 2 mbit (256k x 8) serial flash memory, with advanced write protection mecha- nisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 4 sectors, each con- taining 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as con- sisting of 1024 pages, or 262,144 bytes. the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. figure 2. logic diagram figure 3. so and vdfpn connections note: 1. there is an exposed die paddle on the underside of the mlp8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see package mechanical section for package di- mensions, and how to identify pin-1. table 1. signal names ai04080 s v cc m25p20 hold v ss w q c d 1 ai04081b 2 3 4 8 7 6 5 d v ss c hold q sv cc w m25p20 c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
m25p20 6/39 signal description serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling e dge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be pro- grammed. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s ). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal pro- gram, erase or write status register cycle is in progress, the dev ice will be in the standby mode (this is not the deep power-down mode). driving chip select (s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. hold (hold ). the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be se- lected, with chip select (s ) driven low. write protect (w ). the main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against program or erase instructions (as specified by the values in the bp1 and bp0 bits of the status register).
7/39 m25p20 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 5. , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 4. bus master and memory devices on the spi bus note: the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 5. spi modes supported ai03746d bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m25p20 8/39 operating features page programming to program one data byte, two instructions are re- quired: write enable (wren), which is one byte, and a page program (pp) sequence, which con- sists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be pro- grammed at a time (changing bits from 1 to 0), pro- vided that they lie in consecutive addresses on the same page of memory. sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an internal erase cycle (of duration t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). the write in progress (wip) bit is provided in the status regis- ter so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is com- plete. active power, stand-by power and deep power-down modes when chip select (s ) is low, the device is en- abled, and in the active power mode. when chip select (s ) is high, the device is dis- abled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device re- mains in this mode until another specific instruc- tion (the release from deep power-down mode and read electronic signature (res) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. status register the status register contains a number of status and control bits, as shown in table 5. , that can be read or set (as appropriate) by specific instruc- tions. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits.
9/39 m25p20 protection modes the environments where non-volatile memory de- vices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25p20 boasts the following data protection mechanisms: power-on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the operating specification. program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit . this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion the block protect (bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). the write protect (w ) signal, in co-operation with the status register write disable (srwd) bit, allows the block protect (bp1, bp0) bits and status register write disable (srwd) bit to be write-protected. this is the hardware protected mode (hpm). in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertant write, program and erase instructions, as all instructions are ignored except one particular instruction (the release from deep power- down instruction). table 2. protected area sizes note: 1. the device is ready to accept a bulk erase instruction if, and only if, both block protect (bp1, bp0) are 0. status register content memory content bp1 bit bp0 bit protected area unprotected area 0 0 none all sectors 1 (four sectors: 0, 1, 2 and 3) 0 1 upper quarter (sector 3) lower three-quarters (three sectors: 0 to 2) 1 0 upper half (two sectors: 2 and 3) lower half (sectors 0 and 1) 1 1 all sectors (four sectors: 0, 1, 2 and 3) none
m25p20 10/39 hold condition the hold (hold ) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (s ) low. the hold condition starts on the falling edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low (as shown in fig- ure 6. ). the hold condition ends on the rising edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts af- ter serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low. (this is shown in figure 6. ). during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select (s ) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the mo- ment of entering the hold condition. if chip select (s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart commu- nication with the device, it is necessary to drive hold (hold ) high, and then to drive chip select (s ) low. this prevents the device from going back to the hold condition. figure 6. hold condition activation ai02029d hold c hold condition (standard use) hold condition (non-standard use)
11/39 m25p20 memory organization the memory is organized as: 262,144 bytes (8 bits each) 4 sectors (512 kbits, 65536 bytes each) 1024 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. table 3. memory organization figure 7. block diagram sector address range 3 30000h 3ffffh 2 20000h 2ffffh 1 10000h 1ffffh 0 00000h 0ffffh ai04079 hold s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c d q status register 00000h 10000h 20000h 30000h 3ffffh 000ffh size of the read-only memory area
m25p20 12/39 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 4. . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (s ) must be driven high after the last bit of the instruction se- quence has been shifted in. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read status register (rdsr) or release from deep power-down, and read electronic signature (res) instruction, the shifted-in instruction se- quence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren), write disable (wrdi) or deep power-down (dp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is reject- ed, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are i gnored, and the internal write status register cycle, program cycle or erase cy- cle continues unaffected. table 4. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pp page program 0000 0010 02h 3 0 1 to 256 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 res release from deep power-down, and read electronic signature 1010 1011 abh 0 3 1 to release from deep power-down 0 0 0
13/39 m25p20 write enable (wren) the write enable (wren) instruction ( figure 8. ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set pri- or to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the in- struction code, and then driving chip select (s ) high. figure 8. write enable (wren) instruction sequence write disable (wrdi) the write disable (wrdi) instruction ( figure 9. ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruc- tion code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: ?power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 9. write disable (wrdi) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
m25p20 14/39 read status register (rdsr) the read status register (rdsr) instruction al- lows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status reg- ister continuously, as shown in figure 10. . table 5. status register format the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. bp1, bp0 bits. the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 2. ) becomes protected against page program (pp) and sector erase (se) instructions. the block protect (bp1, bp0) bits can be written pro- vided that the hardware protected mode has not been set. the bulk erase (be) instruction is exe- cuted if, and only if, both block protect (bp1, bp0) bits are 0. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) be- come read-only bits and the write status register (wrsr) instruction is no longer accepted for exe- cution. figure 10. read status register (rdsr) instruction sequence and data-out sequence b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
15/39 m25p20 write status register (wrsr) the write status register (wrsr) instruction al- lows new values to be written to the status regis- ter. before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 11. . the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driv- en high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. at some unspecified time before the cycle is complet- ed, the write enable latch (wel) is reset. the write status register (wrsr) instruction al- lows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 2. . the write status register (wrsr) in- struction also allows the user to set or reset the status register write disable (srwd) bit in ac- cordance with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not execut- ed once the hardware protected mode (hpm) is entered. figure 11. write status register (wrsr) instruction sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m25p20 16/39 table 6. protection modes note: 1. as defined by the values in the block protect (bp1, bp0) bits of the status register, as shown in table 2. . the protection features of the device are summa- rized in table 6. . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in- struction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): ? if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving write protect (w ) low ? or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. w signal srwd bit mode write protection of the status register memory content protected area 1 unprotected area 1 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
17/39 m25p20 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the mem- ory contents, at that address, is shifted out on se- rial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 12. . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is termi- nated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data out- put. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 12. read data bytes (read) instruction sequence and data-out sequence note: address bits a23 to a18 are don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
m25p20 18/39 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 13. . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be contin- ued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driv- en high at any time during data output. any read data bytes at higher speed (fast_read) in- struction, while an erase, program or write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. figure 13. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence note: address bits a23 to a18 are don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
19/39 m25p20 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write en- able latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14. . if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without hav- ing any effects on the other bytes of the same page. chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed page program cycle (whose duration is t pp ) is initiated. while th e page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp1, bp0) bits (see table 3. and table 2. ) is not executed. figure 14. page program (pp) instruction sequence note: address bits a23 to a18 are don?t care. c d ai04082b s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
m25p20 20/39 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decod- ed, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the sector (see table 3. ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15. . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose du- ration is t se ) is initiated. while the sector erase cy- cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp1, bp0) bits (see table 3. and table 2. ) is not executed. figure 15. sector erase (se) instruction sequence note: address bits a23 to a18 are don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
21/39 m25p20 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write en- able latch (wel). the bulk erase (be) instruction is entered by driv- ing chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16. . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not exe- cuted. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed bulk erase cycle, and is 0 when it is com- pleted. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if both block protect (bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 16. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
m25p20 22/39 deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in table 12. ). once the device has entered the deep power- down mode, all instructions are ignored except the release from deep power-down and read elec- tronic signature (res) instruction. this releases the device from this mode. the release from deep power-down and read electronic signature (res) instruction also allows the electronic signa- ture of the device to be output on serial data out- put (q). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the in- struction code on serial data input (d). chip se- lect (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17. . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruc- tion is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is re- jected without having any effects on the cycle that is in progress. figure 17. deep power-down (dp) instruction sequence c d ai03753d s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
23/39 m25p20 release from deep power-down and read electronic signature (res) once the device has entered the deep power- down mode, all instructions are ignored except the release from deep power-down and read elec- tronic signature (res) instruction. executing this instruction takes the device out of the deep pow- er-down mode. the instruction can also be used to read, on serial data output (q), the 8-bit electronic signature, whose value for the m25p20 is 11h . except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (res) instruction always provides access to the 8- bit electronic signature of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read electronic signature (res) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s ) low. the instruction code is followed by 3 dummy bytes, each bit being latched-in on serial data input (d) during the rising edge of serial clock (c). then, the 8-bit electronic signature, stored in the memory, is shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 18. . the release from deep power-down and read electronic signature (res) instruction is terminat- ed by driving chip select (s ) high after the elec- tronic signature has been read at least once. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the electronic signature to be output repeatedly. when chip select (s ) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immedi- ate. if the device was previously in the deep pow- er-down mode, though, the transition to the stand- by power mode is delayed by t res2 , and chip se- lect (s ) must remain high for at least t res2 (max), as specified in table 17. . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instruc- tions. figure 18. release from deep power-down and read electronic signature (res) instruction sequence and data-out sequence note: the value of the 8-bit electronic signature, for the m25p20, is 11h. c d ai04047c s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 765432 0 1 high impedance electronic signature out instruction 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2
m25p20 24/39 figure 19. release from deep power-down (res) instruction sequence driving chip select (s ) high after the 8 - bit instruc- tion byte has been received by the device, but be- fore the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in fig- ure 19. ), still insures that the device is put into stand-by power mode. if the device was not pre- viously in the deep power-down mode, the transi- tion to the stand-by power mode is immediate. if the device was previously in the deep power- down mode, though, the transition to the stand-by power mode is delayed by t res1 , and chip select (s ) must remain high for at least t res1 (max), as specified in table 17. . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. c d ai04078b s 2 1 34567 0 t res1 stand-by mode deep power-down mode q high impedance instruction
25/39 m25p20 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ?v cc (min) at power-up, and then for a further delay of t vsl ?v ss at power-down usually a simple pull-up resistor on chip select (s ) can be used to insure safe and proper power-up and power-down. to avoid data corruption and inadvertent write op- erations during power up, a power on reset (por) circuit is included. the logic inside the de- vice is held reset while v cc is less than the por threshold value, v wi ? all operations are disabled, and the device does not respond to any instruc- tion. moreover, the device ignores all write enable (wren), page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: ?t puw after v cc passed the v wi threshold ?t vsl afterv cc passed the v cc (min) level these values are specified in table 7. . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: ? the device is in the standby mode (not the deep power-down mode). ? the write enable latch (wel) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc feed. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operat- ing voltage, to below the por threshold value, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.) figure 20. power-up timing v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
m25p20 26/39 table 7. power-up timing and v wi threshold note: 1. these parameters are characterized only. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). symbol parameter min. max. unit t vsl 1 v cc (min) to s low 10 s t puw 1 time delay to write instruction 1 10 ms v wi 1 write inhibit voltage 1 2 v
27/39 m25p20 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 8. absolute maximum ratings note: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note 1 c v io input and output voltage (with respect to ground) ?0.6 4.0 v v cc supply voltage ?0.6 4.0 v v esd electrostatic discharge voltage (human body model) 2 ?2000 2000 v
m25p20 28/39 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 9. operating conditions table 10. data retention and endurance note: 1. this is preliminary data table 11. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 20mhz. symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature (device grade 6) ?40 85 c ambient operating temperature (device grade 3) ?40 125 parameter condition min. max. unit erase/program cycles device grade 6 100 000 cycles per sector device grade 3 1 10 000 data retention device grade 6 20 years device grade 3 1 (at 85c) 20 symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf
29/39 m25p20 table 12. dc characteristics table 13. dc characteristics (device grade 3) note: 1. this is preliminary data symbol parameter test condition (in addition to those in table 9. ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 5a i cc3 operating current (read) c=0.1v cc / 0.9.v cc at 40mhz, q = open 8ma c=0.1v cc / 0.9.v cc at 20mhz, q = open 4ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma i cc7 operating current (be) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v symbol parameter test condition (in addition to those in table 9. ) min. 1 max. 1 unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 100 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 50 a i cc3 operating current (read) c=0.1v cc / 0.9.v cc at 40mhz, q = open 8ma c=0.1v cc / 0.9.v cc at 20mhz, q = open 4ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma i cc7 operating current (be) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
m25p20 30/39 table 14. instruction times (device grade 6) table 15. instruction times (device grade 3) note: 1. at 85c 2. this is preliminary data table 16. ac measurement conditions note: output hi-z is defined as the point where data out is no longer driven. figure 21. ac measurement i/o waveform test conditions specified in table 9. and table 16. symbol alt. parameter min. typ. max. unit t w write status register cycle time 5 15 ms t pp page program cycle time 1.4 5 ms t se sector erase cycle time 0.8 3 s t be bulk erase cycle time 2.5 6 s test conditions specified in table 9. and table 16. symbol alt. parameter min. typ. 1,2 max. 2 unit t w write status register cycle time 8 15 ms t pp page program cycle time 1.5 5 ms t se sector erase cycle time 1 3 s t be bulk erase cycle time 2.8 6 s symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v ai07455 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels 0.5v cc
31/39 m25p20 table 17. ac characteristics (25mhz operation, device grade 6 or 3) note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. test conditions specified in table 9. and table 16. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 25 mhz f r clock frequency for read instructions d.c. 20 mhz t ch 1 t clh clock high time 18 ns t cl 1 t cll clock low time 18 ns t clch 2 clock rise time 3 (peak to peak) 0.1 v/ns t chcl 2 clock fall time 3 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 10 ns t chsl s not active hold time (relative to c) 10 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 10 ns t shch s not active setup time (relative to c) 10 ns t shsl t csh s deselect time 100 ns t shqz 2 t dis output disable time 15 ns t clqv t v clock low to output valid 15 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 10 ns t chhh hold hold time (relative to c) 10 ns t hhch hold setup time (relative to c) 10 ns t chhl hold hold time (relative to c) 10 ns t hhqx 2 t lz hold to output low-z 15 ns t hlqz 2 t hz hold to output high-z 20 ns t whsl 4 write protect setup time 20 ns t shwl 4 write protect hold time 100 ns t dp 2 s high to deep power-down mode 3 s t res1 2 s high to standby mode without electronic signature read 3 s t res2 2 s high to standby mode with electronic signature read 1.8 s
m25p20 32/39 table 18. ac characteristics (40mhz operation, device grade 6) note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. details of how to find the date of marking are given in application note, an1995 . 40mhz available for products marked since week 20 of 2004, only 5 test conditions specified in table 9. and table 16. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 40 mhz f r clock frequency for read instructions d.c. 20 mhz t ch 1 t clh clock high time 11 ns t cl 1 t cll clock low time 11 ns t clch 2 clock rise time 3 (peak to peak) 0.1 v/ns t chcl 2 clock fall time 3 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz 2 t dis output disable time 9 ns t clqv t v clock low to output valid 9 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx 2 t lz hold to output low-z 9 ns t hlqz 2 t hz hold to output high-z 9 ns t whsl 4 write protect setup time 20 ns t shwl 4 write protect hold time 100 ns t dp 2 s high to deep power-down mode 3 s t res1 2 s high to standby mode without electronic signature read 3 s t res2 2 s high to standby mode with electronic signature read 1.8 s
33/39 m25p20 figure 22. serial input timing figure 23. write protect setup and hold timing during wrsr when srwd=1 c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w twhsl tshwl ai07439
m25p20 34/39 figure 24. hold timing figure 25. output timing c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz c q ai01449d s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
35/39 m25p20 package mechanical figure 26. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. table 19. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27??0.050?? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
m25p20 36/39 figure 27. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package outline note: drawing is not to scale. table 20. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 0.85 1.00 0.0335 0.0394 a1 0.00 0.05 0.0000 0.0020 a2 0.65 0.0256 a3 0.20 0.0079 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 6.00 0.2362 d1 5.75 0.2264 d2 3.40 3.20 3.60 0.1339 0.1260 0.1417 e 5.00 0.1969 e1 4.75 0.1870 e2 4.00 3.80 4.20 0.1575 0.1496 0.1654 e 1.27 0.0500 l 0.60 0.50 0.75 0.0236 0.0197 0.0295 12 12 d e vdfpn-01 a2 a a3 a1 e1 d1 e e2 d2 l b
37/39 m25p20 part numbering table 21. ordering information scheme note: 1. st strongly recommends the use of the automotive grade devices for use in an automotive environment. the high reliabilit y cer- tified flow (hrcf) is described in the quality note qnee9801. please ask your nearest st sales office for a copy. 2. available for so8 package only 3. available for mlp package only 4. device grade 3 available in so8 lead-free and rohs compliant package for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. example: m25p20 ? v mn 6 t p device type m25p = serial flash memory for code storage device function 20 = 2 mbit (256k x 8) operating voltage v = v cc = 2.7 to 3.6v package mn = so8 (150 mil width) mp = vdfpn8 6x5mm (mlp8) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 4 = device tested with high reliability certified flow 1 . automotive temperature range (?40 to 125 c) option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p 2 = lead-free and rohs compliant g 3 = lead-free, rohs compliant, sb 2 o 3 -free and tbba-free
m25p20 38/39 revision history table 22. document revision history date rev. description of revision 12-apr-2001 1.0 document written 25-may-2001 1.1 serial paged flash memory renamed as serial flash memory 11-sep-2001 1.2 changes to text: signal description/chip select; hold condition/1st para; protection modes; release from power-down and read electronic signature (res); power-up repositioning of several tables and illustrations without changing their contents power-up timing illustration; so8w package removed changes to tables: abs max ratings/v io ; dc characteristics/v il 16-jan-2002 1.3 fast_read instruction added. document revised with new timings, v wi , i cc3 and clock slew rate. descriptions of polling, hold condition, page programming, release for deep power- down made more precise. value of t w (max) modified. 16-may-2002 1.4 clarification of descriptions of entering stand-by power mode from deep power-down mode, and of terminating an instruction sequence or data-out sequence. 12-sep-2002 1.5 vfqfpn8 package (mlp8) added. document promoted to full datasheet. 13-dec-2002 1.6 typical page program time improved. write protect setup and hold times specified, for applications that switch write protect to exit the hardware protection mode immediately before a wrsr, and to enter the hardware protection mode again immediately after. 24-nov-2003 2.0 table of contents, warning about exposed paddle on mlp8, and pb-free options added. 40mhz ac characteristics table included as well as 25mhz. i cc3 (max), t se (typ) and t be (typ) values improved. change of naming for vdfpn8 package 26-apr-2004 3.0 automotive range added. soldering temperature information clarified for rohs compliant devices. device grade clarified 05-aug-2004 4.0 device grade information clarified. data-retention measurement temperature corrected. details of how to find the date of marking added.
39/39 m25p20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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